![PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/4492954219035e0111652e49d71aa2eff9cea775/4-Figure4-1.png "PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar")
PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar
Lab 3
Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors - ScienceDirect
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![PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/4492954219035e0111652e49d71aa2eff9cea775/3-Figure2-1.png "PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar")
PDF] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | Semantic Scholar
Electronics | Free Full-Text | An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation | HTML
Logical circuit implementing an SRAM cell. | Download Scientific Diagram
Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors - ScienceDirect
